One type of passive component that is increasingly incorporated into many IC designs is a MIM capacitor, which typically incorporates a stacked arrangement of materials that comprises top and bottom electrically conductive electrodes, and an intermediate insulator layer incorporating one or more dielectric layers. Typically, a MIM capacitor is fabricated between metal interconnect layers in an IC (e.g., between the M2 and M3 layer), which locates the MIM capacitor away from the underlying semiconductor surface, such that parasitic capacitance effects with the semiconductor surface of the substrate are minimized.
Given the ever-present desire to reduce the sizes of components in an IC, it is desirable to minimize the circuit area occupied by MIM capacitors. To provide a desired capacitance from a MIM capacitor within a smaller circuit area, an increase in the capacitance density of the capacitor (which based upon present design rules is typically expressed in terms of femtofarads per square micrometer (fF/μm2)) is generally relied on. Conventional approaches for increasing MIM capacitor capacitance density have typically focused upon using high dielectric constant (high-k) dielectric materials in the dielectric layer of the MIM capacitor, decreasing the dielectric layer thickness and/or utilizing capacitor geometries that increase the perimeter (which increases fringe and lateral capacitance effects). High-k dielectric constant materials such as tantalum pentoxide, tantalum oxynitride, silicon nitride, barium strontium titanate (BST), lead zirconium titanate, and hafnium oxide have been used in conventional MIM capacitor designs. The dielectric thickness can be in a range of approximately 200 to 500 A, with the minimum thickness generally selected to limit short circuits or leakage between the top and bottom electrodes of the MIM capacitor.
The MIM capacitor has low resistivity and no parasitic capacitance caused by depletion (assuming metal electrodes, as opposed to polysilicon electrodes), so it is widely used in high performance semiconductor devices that benefit from a high Q value. MIM capacitors are often utilized, for example, in high frequency (e.g., RF) telecommunications applications, such as in cellular phones and other wireless devices, as well as other telecommunications products. Often, MIM capacitors are used to provide functions such as decoupling with a power supply, analog functions such as analog-to-digital conversions (ADC) and filtering, and termination of transmission lines. Decoupling applications generally have relatively loose leakage requirements, whereas analog applications, such as for ADC's, typically require closer capacitor matching (e.g., between neighboring capacitors), and relatively good voltage linearity. For analog technology nodes needing high density, high precision TiN—Al or TiN/Ti/TiN—Al interconnect metal capacitors have been used that have a top electrode thickness generally between 1,500 and 2,000 A and a dielectric thickness of about 200 to 400 A. For such capacitors, the dielectric can comprise Si3N4 (silicon nitride) or SiON (silicon oxynitride), which can be used as a non-sacrificial layer in the regions outside the MIM capacitor to function as an anti-reflective coating (ARC) for subsequent lithography. In one embodiment, SiON may be interposed between silicon oxide layers as silicon oxide (capping layer)/SiON/silicon oxide (bottom layer).
Processing for defining such MIM capacitors generally involves etching of the top electrode layer and attempting to preserve the underlying dielectric layer, such as in order to serve as an ARC layer. As a consequence, a highly selective top electrode: dielectric etch process is generally needed. Known reasonably selective top electrode etch chemistries generally comprise at least in part wet etching, which necessitates the use of hard masking layers (e.g., silicon nitride), which adds to process complexity, cycle time and cost as compared to soft masking (resist) layers which can be used with dry (e.g., plasma) etch processes.